The present invention relates to a programmable digital delay generator and particularly to such a generator for indicating an accurate delay period without the presence of time variations or jitter in the output signal.
A programmable delay generator is one that finds use, for example, in a digital oscilloscope wherein a multiplicity of samples of an input signal are taken at digitally adjustable times. These samples of the input signal are digitally stored and may be read out at a slower rate for display on a cathode-ray tube.
Successive samples of an input signal can be taken at times which may change with respect to an input triggering signal and these times are suitably determined by means of a digital counter. For example, the counter may be preloaded with different numbers after which the counter steps to a predetermined terminal count that is detected for generating a desired signal sampling pulse.
Heretofore, synchronous counters have been employed for sample timing purposes because of their accuracy of operation and the speed with which they change from one count to the next. A synchronous counter is characterized by a common clock pulse which causes all counter stages to change state (if they are otherwise enabled) at the same time. Then, when the counter reaches a predetermined terminal count, this terminal count is rapidly detected for setting the time that signal sampling is to take place.
Although all the stages of a synchronous counter are clocked by the safe clock signal and are supposed to change states at the same time, this in fact is not realized. Moreover, clock distribution may be a problem in a fast counter.
In a given synchronous counter of given circuit configuration some undetermined stage may change states before some other stage, and as a matter of fact all the stages may change state at times which are unpredictably different. Therefore, since the counter stages do not in fact operate in synchronism when measured on an accurate time scale, the sampling pulses generated thereby may not occur at accurately predetermined times, or at times properly interrelated to other sampling pulses. Consequently, even though the construction of a synchronous counter is comparatively complex and expensive, the timing information derived therefrom may be inaccurate and undependable. The result is improper sampling operation and jitter at high speeds.